1. Field of the Invention
The present invention relates to a coating and developing apparatus, and a coating and developing method, which perform a coating process of applying a resist liquid or the like to a substrate, such as a semiconductor wafer or a glass substrate for liquid crystal display (LCD substrate), and a developing process on the substrate after exposure.
2. Description of the Related Art
In a fabrication process of a semiconductor device or an LCD substrate, a resist pattern is formed on a substrate using a technology called photolithography. According to the technology, a resist liquid is applied to the top surface of a substrate, such as a semiconductor wafer, to form a liquid film, which is then dried to be a resist film, the resist film is exposed into a desired pattern using a photomask, and then a developing process is performed to yield a resist pattern corresponding to the exposure pattern.
Such a sequence of processes is generally carried out by using a resist pattern forming apparatus that has an exposure apparatus connected to a coating and developing apparatus which applies and dries a resist liquid. One example of such an apparatus is disclosed in Unexamined Japanese Patent Application KOKAI Publication No. 2004-193597.
The apparatus disclosed in the publication includes a carrier block 1A, a process block 1B, an interface block 1C and an exposure apparatus 1D, as shown in FIG. 1. In the apparatus, carriers 10 each retaining multiple wafers W are carried onto a carrier stage 11 of the carrier block 1A, and the wafers in the carrier 10 are transferred to the process block 1B. Then, the wafers are transferred to a coating unit 13a in the process block 1B, a resist liquid is applied to the wafers, and then the wafers are transferred the exposure apparatus 1D via the interface block 1C. The wafers after exposure are returned to the process block 1B again, and are transferred to a developing unit 13b to undergo a developing process, after which the wafers are returned into the original carrier 10.
Referring to FIG. 1, reference numerals 14a to 14c denote shelf units which comprise a multilevel of heating units, cooling units, transfer stages and so forth for performing a predetermined heating process and cooling process on wafers before and after the processing of the coating unit 13a and the processing of the developing unit 13b. The wafers W are transferred between modules in the process block 1B where the wafers W are to be placed, such as individual sections like the coating unit 13a, the developing unit 13b and the.shelf units 14a to 14c, by two transfer devices 15a and 15b provided in the process block 1B. The interface block 1C is provided with transfer mechanisms 16a and 16b which transfer wafers W between the process block 1B and the exposure apparatus 1D.
Unexamined Japanese Patent Application KOKAI Publication No. 2004-193597 describes that at the time wafers W are subjected to the processes, all the wafers W to be processed are transferred according to a transfer schedule that specifies at which timing each wafer is to be transferred to which module.
The transfer schedule is made in such a way that after a wafer W is transferred to modules, which perform processes preceding exposure, in order using the two transfer devices 15a and 15b in the process block 1B, the wafer is then transferred to the interface block 1C, and a wafer after exposure is received from the interface block 1C and is transferred to modules, which perform processes following exposure, in order. As the transfer devices 15a and 15b go round in the process block 1B, one transfer cycle is executed, and a new wafer W carried out from the carrier 10 is transferred into the process block 1B every transfer cycle.
Such a resist pattern forming apparatus may come across a case where the a wafer W cannot be received from the process block 1B or cannot be transferred to the process block 1B at the timing set in the transfer schedule upon occurrence of some kind of abnormality, such as failure of the transfer mechanisms 16a and 16b provided in the interface block 1C, or collision of the transfer mechanisms 16a and 16b against the transfer stage, or slight delay in carrying out a wafer from the exposure apparatus 1D.
According to the resist pattern forming apparatus described in the Japanese publication, when such a situation occurs, the operations of the transfer devices 15a and 15b are stopped for the following reason. As the transfer program is complex, if the transfer devices 15a and 15b are allowed to retreat in the transfer path, the transfer program becomes extremely complicated, which is not practical.
If the transfer devices 15a and 15b stop, however, a wafer W is not removed from each module and is left inside the module. If a wafer W is left remaining in a module this way, various problems occur. When a wafer W processed in the coating unit 13a is left remaining in the coating unit 13a, for example, the quality of the coated resist film is degraded, so that even when wafer transfer with the transfer devices 15a and 15b is resumed thereafter, the predetermined quality of the resist film cannot be guaranteed. A wafer W left inside each module often hardly meets a predetermined quality, in which case the wafer cannot be delivered as a product, thus reducing the yield.
With the recent improvement of the throughput of exposure apparatuses, a coating and developing apparatus is demanded of the processing performance that matches with the throughput of exposure apparatuses. One possible approach studied is to arrange an area to store modules before exposure and an area to store modules after exposure, one above the other, and provide transfer means in each area to lower the load of the transfer means and enhance the transfer efficiency, thereby improving the throughput of exposure apparatuses. Japanese Patent No. 3337677, for instance, discloses the structure where an area for performing a coating process and an area for performing a developing process are laid one on the other and transfer means is provided in each area.
Even with the structure, wafers W are transferred between the coating and developing apparatus and the exposure apparatus by a transfer mechanism provided in the interface block, and wafers W are transferred in each area according to the transfer schedule by a transfer mechanism provided in that area. When some kind of abnormality occurs in the transfer mechanism provided in the interface block, therefore, the aforementioned problem may come up. The publication gives no description of any means to overcome the problem.